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● Provides a user-definable, 56-line parallel interface with bit, byte, pulse, string and binary data transfer capabilities. Fully configurable to the user's needs by bus commands. ● High-current drivers and input pullup resistors. Drives more devices, longer lines and inputs CMOS signals or switch contacts. ● Signal monitor feature detects and reports signal changes on 15 inputs. Relieves controller of time consuming polling. ● Device configuration, user's IDN message and bus address stored in Flash. Stored setup eliminates program initialization statements. ● Lock feature prevents accidental loss or change of user configuration. Protects your configuration and IDN message. ● Packaged on 3U VME size card with 4823A pinouts. Can be used to replace 4823A cards in 56 line applications.
The Model 4823B GPIB <-> Digital Interface Board is an IEEE-488.2/GPIB to digital interface with 56 I/O lines that can be used to easily adapt devices with digital signals to the IEEE-488/GPIB or HP-IP bus. In a typical application, the ICS Digital Interface Board 4823B is located inside the device chassis and is powered by the device's +5 volt power. All digital signal connections are on a 96-pin right-angle DIN connector at one end of the card. A 26-pin header on the other end of the ICS Digital Interface Board 4823B contains the GPIB Bus and address switch input signals. The header connects to a companion GPIB Connector/Address Switch Board that mounts a GPIB Connector and Address Switch on the rear panel of the chassis.
ICS Digital Interface Board 4823B are also available with optional vertical and circuit-side DIN connectors to facilitate piggybacking the 4823B on a larger PC board. The 4823B's pinouts match the first 56 pins of ICS's earlier 4823A card so that the 4823B can be used as a replacement for the 4823A in applications that use no more than 56 I/O lines.
Dual primary addresses or single primary with secondary addresses 0 and 1.
Primary address range: 0-30.
SRQ Generation
SRQs are generated if the unit is not a talker, if SRQs are enabled and if an Enabled Event Status Register bit or if a monitored digital input change occurs. Digital inputs monitored by the Questionable registers.
Used to set and query all programmable functions. The 4823B conforms to SCPI 1994.0 Specification.
Interface Specifications
Signal Characteristics
The 4823B's parallel I/O signals have the following electrical characteristics. All time delays listed here are maximums, all pulse widths are minimums.
Inputs
56 Digital I/O, 2 Status and Reset Inputs
Input Logic Levels
High = > +2.0 V @ ±10 μA
Low = <0.8 V @ 250 μA
with 33 KΩ pullup to +5 VDC for sensing contacts.
Max high input = 5.5 V
Input Timing
External Data Inhibit line SETS within 1 μs of the active edge of the EDR Input signal and resets after data is loaded. Data loading time for 6 BCD/HEX characters is 0.15 ms (typ.) after the 4823B has been addressed as a Talker.
Output Logic Levels
High = >3 V with 3 mA source
High =>2 V with 24 mA source
Low = 0.0 to +0.55 Vdc, 48 mA sink
Output Timing
Data is transferred to the output 0.6 to 5.3 ms after receipt of a terminator depending upon transfer method.
Data Stb
Output pulse width, 5 μs
Trigger
Output pulse width, 5 μs
Remote
Output level asserted when in the remote state
Reset
Output pulse width, 40 μs for *RST command and true during 4823B reset time (70 ms)
Digital Input
Reset Inputs
The 4823B is reset by a low going pulse on the External Reset input line or by pressing a miniature push-button on front edge of the 4823B's PCB